Method and apparatus for analyzing integrated circuit operations
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United States of America Patent
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Aug 18, 2009
Grant Date -
Dec 28, 2006
app pub date -
Jun 23, 2005
filing date -
Jun 23, 2005
priority date (Note) -
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Abstract
A method and apparatus for viewing and/or analyzing the operations and logical states of an integrated circuit. The logical state of various flip-flops within the ASIC may be determined at a specified time. The embodiment may store these flip-flop states in a computer-readable data structure, such as a file or database. By repeating this process and incrementing or decrementing the time with each repetition, a more complete picture of the ASIC's operation may be captured. Additionally, the embodiment may graphically display the flip-flop states, for example as a graph or waveform.
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