System for a memory device having a power down mode and method
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United States of America Patent
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Aug 25, 2009
Grant Date -
Oct 20, 2005
app pub date -
Jun 14, 2005
filing date -
Mar 10, 1998
priority date (Note) -
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Abstract
A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.
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