Interface circuit system and method for performing power saving operations during a command-related latency
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United States of America Patent
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Aug 25, 2009
Grant Date -
Feb 14, 2008
app pub date -
Oct 20, 2006
filing date -
Jul 31, 2006
priority date (Note) -
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Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.
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