Semiconductor die package with internal bypass capacitors
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United States of America Patent
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Sep 1, 2009
Grant Date -
Jan 29, 2009
app pub date -
Sep 30, 2008
filing date -
Jun 17, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
Embodiments of the present invention provide a computer system that reduces voltage noise for a processor chip. The computer system includes a package which is configured to be sandwiched between the processor chip and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the processor chip. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the processor chip, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.
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