Systems and methods for multi-tasking, resource sharing, and execution of computer instructions
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United States of America Patent
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Sep 15, 2009
Grant Date -
Oct 7, 2004
app pub date -
Apr 14, 2004
filing date -
Apr 3, 1998
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Abstract
In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.
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Patent Owner(s)
- CLEARWATER INNOVATIONS, LLC
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Joffe, Alexander | Palo Alto , US | 35 | 1181 |
Vyshetsky, Dmitry | Cupertino , US | 21 | 544 |
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