Microprocessor and method of processing instructions for responding to interrupt condition
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United States of America Patent
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Sep 22, 2009
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N/A
app pub date -
Nov 15, 2002
filing date -
Nov 15, 2002
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Abstract
A pipeline processing microprocessor includes a storage unit for storing instructions and a fetch unit for requesting and fetching an instruction from the instructions in the storage unit. Upon an interrupt condition, the fetch unit eliminates from a request queue a previously requested instruction that precedes the interrupt condition.
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