Low stress thin film microshells

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7595209
SERIAL NO

11716233

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Abstract

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Multi-layered, planar microshells having low stress for encapsulation of devices such as MEMS and microelectronics. The microshells may include a perforated pre-sealing layer, below which a sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may further include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. The various layers may be formed employing processes having opposing stresses to tune the residual stress of the multi-layered microshell. In an embodiment, the hermetic layer is a metal which is deposited with a process tuned to impart a tensile stress to lower the residual stress in the microshell below the magnitude of cumulative stress present in sealing layer and pre-sealing layer.

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Patent Owner(s)

Patent OwnerAddress
SILICON LABORATORIES INC400 W CESAR CHAVEZ AUSTIN TX 78701

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Howe, Roger T Los Gatos , US 68 4561
Monadgemi, Pezhman Fremont , US 44 1134
Quevy, Emmanuel P El Cerrito , US 52 1159

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