Overlay vernier of semiconductor device and method of manufacturing the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 29, 2009
Grant Date -
Jul 3, 2008
app pub date -
May 24, 2007
filing date -
Dec 28, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
After a mother vernier pattern is formed in a scribe region of a semiconductor substrate, a child vernier pad is formed on the inner region of a mother vernier, and a child vernier is formed on the child vernier pad in order to obviate the step of the mother vernier. Thus, at the time of an exposure process for forming the child vernier, failure of the pattern due to the step can be prevented and alignment can be measured accurately.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully