Integrated memory controller
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United States of America Patent
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Sep 29, 2009
Grant Date -
N/A
app pub date -
Oct 4, 2006
filing date -
Jun 14, 2004
priority date (Note) -
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Abstract
A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) comprises logic for managing programmable clock signal relationships such that data that is read from the DDR is centered within a DQS signal which is generated from the DDR and then appropriately delayed.
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