Delay locked loop implementation in a synchronous dynamic random access memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 6, 2009
Grant Date -
Dec 1, 2005
app pub date -
Aug 1, 2005
filing date -
Oct 6, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully