Wire-speed packet management in a multi-pipeline network processor
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United States of America Patent
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Oct 6, 2009
Grant Date -
Jan 5, 2006
app pub date -
Jul 2, 2004
filing date -
Jul 2, 2004
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Abstract
A flow-identification content addressable memory (FICAM) comprising a row of content addressable memory (CAM) cells operable to store a first flow-identification. The first flow-identification corresponds to a first packet dispatched for processing by a pipeline unit (PU) belonging to a network processor. A comparison unit compares a second flow-identification corresponding to a second packet with contents of said at least a row of CAM cells. The comparison unit is further capable of determining if the second flow-identification is same as the first flow-identification. A flow identification eraser is provided for removing the first flow-identification from said at least a row of CAM cells upon determination by the comparison unit that the second flow-identification is same as the first flow-identification.
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