Circuit having relaxed setup time via reciprocal clock and data gating
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United States of America Patent
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Oct 6, 2009
Grant Date -
Jun 12, 2008
app pub date -
Dec 7, 2006
filing date -
Dec 7, 2006
priority date (Note) -
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Abstract
An integrated circuit includes a circuit output, a data input that receives a data signal, and a clock input that receives a clock signal. The integrated circuit further includes first and second logic gates. The first logic gate has a first input coupled to the clock input, a second input coupled to the data input, and an output and a second logic gate. The second logic gate has a first input coupled to the data input, a second input coupled to the output of the first logic gate, and an output coupled to the circuit output. Setup time of the data signal relative to the clock signal at the second logic gate is improved by reciprocal gating of the data and clock signals.
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