Read operation for NAND memory
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United States of America Patent
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Oct 20, 2009
Grant Date -
Oct 25, 2007
app pub date -
Apr 19, 2006
filing date -
Apr 19, 2006
priority date (Note) -
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Abstract
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of memory cells and a second, different, potential is supplied to other source lines not associated with that block. By supplying a different potential to source lines of unselected blocks, current leakage can be mitigated.
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