Probeless DC testing of CMOS I/O circuits

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7609079
APP PUB NO 20070208526A1
SERIAL NO

11366742

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method and implementation is described by which I/O input and output circuitry of a CMOS chip are measured without the need to probe the chip. Output driver transistors are used to provide marginal voltages to test input circuits, and the output driver transistors are segmented into portions where a first portion is used to provide a representative “on” current, which is coupled to a test bus that is further connected to a current comparator circuit contained within the chip. Both leakage and “on” current of the driver transistors is measured using segmented driver transistors. The output of the current comparator circuit is connected to a test scan register or to a test output from which test results are obtained digitally. The testing techniques are also applicable for other semiconductor devices.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
DIALOG SEMICONDUCTOR GMBHKIRCHHEIM/TECK-NABERN

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Coffey, Tony Highworth , GB 3 44
Von, Staudt Hans Martin Weilheim , DE 10 49

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation