Non-volatile memory with background data latch caching during erase operations
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United States of America Patent
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Oct 27, 2009
Grant Date -
Oct 19, 2006
app pub date -
May 5, 2006
filing date -
Apr 1, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with an erase operation. In the exemplary embodiment, a read operation is inserted just prior to the erase operation or one or more read operations are inserted during a soft programming phase of the erase operation. In this way, the read data could be output while the erase operation is taking place, thereby making use of otherwise waiting time.
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