Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution
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United States of America Patent
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Nov 10, 2009
Grant Date -
May 10, 2007
app pub date -
Dec 22, 2006
filing date -
Feb 21, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one parameter. The virtual instruction expansion store includes at least one instruction template and at least one parameter selector. The substitution logic forms a sequence of at least one expanded instruction. In an example, each expanded instruction is based on an instruction template and includes a new parameter for use with the instruction template. The new parameter is generated by performing a logical operation from the parameter selector on one or more parameter of the virtual instruction.
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