Memory cell device with coplanar electrode surface and method
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United States of America Patent
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Nov 17, 2009
Grant Date -
Aug 7, 2008
app pub date -
Jan 31, 2008
filing date -
Feb 2, 2007
priority date (Note) -
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Abstract
A memory device described herein includes a bit line having a top surface and a plurality of vias. The device includes a plurality of first electrodes each having top surfaces coplanar with the top surface of the bit line, the first electrodes extending through corresponding vias in the bit line. An insulating member is within each via and has an annular shape with a thickness between the corresponding first electrode and a portion of the bit line acting as a second electrode. A layer of memory material extends across the insulating members to contact the top surfaces of the bit line and the first electrodes.
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