Via programmable gate array with offset bit lines
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United States of America Patent
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Dec 1, 2009
Grant Date -
N/A
app pub date -
Jul 27, 2007
filing date -
Nov 11, 2005
priority date (Note) -
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Abstract
Some embodiments of the invention provide a via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. At least some of the configurable circuits are via programmable (“VP”) configured circuits. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and columns. This circuit arrangement also includes several bit lines, where at least one the bit line provides a configuration value to at least one configurable circuit. In some embodiments, at least some bit lines traverse along more than one column or row in the circuit arrangement.
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