Clock control hierarchy for integrated microprocessors and systems-on-a-chip
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United States of America Patent
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Dec 1, 2009
Grant Date -
Jul 19, 2007
app pub date -
Oct 4, 2005
filing date -
Oct 4, 2005
priority date (Note) -
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Abstract
A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous “chip hold” signal and asynchronous latch/functional unit hold signals to individually target functional units and latches that are to remain in a held state once the “chip hold” state is released. With the present invention, a chip hold request is first activated followed by scannable latch and non-scannable latch hold requests being activated to identify which latches will be clocked or not clocked when the chip hold is released. Functional unit hold signals are activated to place certain ones of the functional units of the chip in a hold state. The chip hold request is deactivated and the chip operates with the selected functional units and latches being maintained in a held state.
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