Single latch data circuit in a multiple level call non-volatile memory device
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United States of America Patent
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Dec 8, 2009
Grant Date -
Oct 30, 2008
app pub date -
Jul 10, 2008
filing date -
Feb 15, 2006
priority date (Note) -
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Abstract
A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
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