Fabrication of hybrid substrate with defect trapping zone

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United States of America Patent

PATENT NO 7632739
APP PUB NO 20080171443A1
SERIAL NO

11836527

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Abstract

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A process for fabricating a hybrid substrate that has a defect trapping zone. The process includes the steps of forming or depositing a first insulator layer on a first substrate of semiconductor material; increasing roughness of the first insulator layer surface; depositing a second insulator layer on the roughened surface of the first insulator to form a trapping zone between the layers; bonding a second substrate onto the second insulator layer by molecular adhesion; and transferring an active layer formed by the implantation of atomic species into one of the substrates. The trapping zone is able to retain gaseous species present at the various interfaces of the hybrid substrate to limit the formation of defects on the surface of the active layer that is transferred.

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Patent Owner(s)

  • SOITEC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hebras, Xavier Grenoble , FR 7 174

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