Field-effect-transistor multiplexing/demultiplexing architectures
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United States of America Patent
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Dec 15, 2009
Grant Date -
Oct 18, 2007
app pub date -
Jun 19, 2007
filing date -
Apr 30, 2004
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Abstract
This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures are disclosed that use alignment-independent processing steps. One of these processes uses one, low-accuracy imprinting step and further alignment-independent processing steps.
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