Flash memory array with independently erasable sectors
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United States of America Patent
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Dec 22, 2009
Grant Date -
N/A
app pub date -
Jul 17, 2006
filing date -
Jul 17, 2006
priority date (Note) -
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Abstract
Systems and methods are disclosed herein to provide a flash memory array with independently erasable sectors. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a multi-sector flash memory array comprising first and second subarrays of flash memory cells. First and second sets of word lines are connected with control gates of the flash memory cells of the first and second subarrays. A first set of row drivers connected with the first set of word lines are adapted to selectively tri-state or drive the first set of word lines with a first voltage. A second set of row drivers connected with the second set of word lines are adapted to selectively tri-state or drive the second set of word lines with the first voltage. A plurality of bitlines are connected with flash memory cells of the first and second subarrays.
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