Packaged semiconductor chip comprising an integrated circuit chip ablated with laser and cut with saw blade from wafer
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United States of America Patent
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Jan 5, 2010
Issued Date -
N/A
app pub date -
Jul 13, 2007
filing date -
Feb 18, 2005
priority date (Note) -
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Abstract
A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.
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