Process for erasing chalcogenide variable resistance memory bits
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United States of America Patent
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Jan 5, 2010
Grant Date -
Dec 18, 2008
app pub date -
May 7, 2007
filing date -
Jul 8, 2005
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Abstract
A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less than a fixed voltage of the substrate. The applied voltage induces an erase current to flow from the p-doped substrate through the n-well and through the variable resistance memory element.
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