Method of fabricating module having stacked chip scale semiconductor packages
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United States of America Patent
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Jan 12, 2010
Grant Date -
Sep 11, 2008
app pub date -
May 22, 2008
filing date -
Jun 20, 2005
priority date (Note) -
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Abstract
Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire bonding between the first and second package substrates.
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