Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches
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United States of America Patent
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Jan 12, 2010
Grant Date -
Mar 20, 2008
app pub date -
Sep 19, 2006
filing date -
Sep 19, 2006
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Abstract
In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes cells with this structure, as an example. A NAND array of memory cells is another example of an application of this cell structure. The memory cell and array structures have wide application to various specific NOR and NAND memory cell array architectures.
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