Semiconductor integrated circuit having a (BIST) built-in self test circuit for fault diagnosing operation of a memory
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United States of America Patent
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Jan 26, 2010
Grant Date -
Jan 24, 2008
app pub date -
Jul 6, 2007
filing date -
Jul 7, 2006
priority date (Note) -
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Abstract
According to the present invention, there is provided a semiconductor integrated circuit having: a BIST including a data generator, an address generator, a control signal generator, a result analyzer, a BIST controller, and a diagnostic data storage circuit including a first capture register which captures and outputs, in accordance with a first clock, a latest address signal and the BIST state signal output from said BIST controller while the flag signal is in as state that no fault is detected, and maintains outputs when the flag signal is in a state that a fault is detected. The semiconductor integrated circuit can further include a memory collar having a memory cell, a second capture register, a comparator, and a flag register. The semiconductor integrated circuit can perform a fault diagnosing operation of a memory by using a comparator type BIST circuit.
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