Distributed memory in field-programmable gate array integrated circuit devices
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United States of America Patent
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Feb 2, 2010
Grant Date -
Sep 25, 2008
app pub date -
May 30, 2008
filing date -
Dec 27, 2005
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Abstract
Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.
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