US Patent No: 7,657,877

Number of patents in Portfolio can not be more than 2000

Method for processing data

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ALSO PUBLISHED AS: 20040243984
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Abstract

A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
KRASS, MAREN, MS.ZURICH54
RICHTER, THOMAS, MR.ZURICH54

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cardoso, Joao Manuel Paiva Vila Nova de Paiva, PT 3 44
May, Frank Zurich, CH 39 302
Nückel, Armin - 15 58
Vorbach, Martin Karlsruhe, DE 148 2032
Weinhardt, Markus Munchen, DE 11 195

Cited Art

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OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (8)
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2009/0132,648 CONTENT DELIVERY AND GLOBAL TRAFFIC MANAGEMENT NETWORK SYSTEM 2009
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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
RICHTER, THOMAS, MR. (12)
7,996,827 Method for the translation of programs for reconfigurable architectures 3 2002
8,429,385 Device including a field having function cells and information providing cells controlled by the function cells 0 2002
8,281,108 Reconfigurable general purpose processor having time restricted configurations 0 2003
8,127,061 Bus systems and reconfiguration methods 0 2003
8,156,284 Data processing method and device 1 2003
8,301,872 Pipeline configuration protocol and configuration unit communication 0 2005
8,250,503 Hardware definition method including determining whether to implement a function as hardware or software 0 2007
8,209,653 Router 0 2008
8,099,618 Methods and devices for treating and processing data 1 2008
8,145,881 Data processing device and method 1 2008
8,069,373 Method for debugging reconfigurable architectures 0 2009
8,058,899 Logic cell array and bus system 1 2009
 
CADENCE DESIGN SYSTEMS, INC. (2)
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INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
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ORACLE INTERNATIONAL CORPORATION (1)
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PACT INFORMATIONSTECHNOLOGIE GMBH (1)
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SONY COMPUTER ENTERTAINMENT INC. (1)
7,950,003 Heads-up-display software development tool for analyzing and optimizing computer software 2 2007
 
TEXAS INSTRUMENTS INCORPORATED (1)
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OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (6)
8,312,301 Methods and devices for treating and processing data 0 2009
8,281,265 Method and device for processing data 0 2009
8,312,200 Processor chip including a plurality of cache elements connected to a plurality of processor cores 0 2010
8,195,856 I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures 0 2010
8,310,274 Reconfigurable sequencer structure 0 2011
8,407,525 Method for debugging reconfigurable architectures 0 2011

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