Process for manufacturing semiconductor integrated circuit device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7659201
APP PUB NO 20080233736A1
SERIAL NO

12127564

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATIONTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hinode, Kenji Hachiouji, JP 22 492
Homma, Yoshio Hinode-machi, JP 53 1300
Imai, Toshinori Ome, JP 35 439
Kondo, Seiichi Kokubunji, JP 49 659
Noguchi, Junji Ome, JP 73 1391
Ohashi, Naofumi Hannou, JP 148 697
Owada, Nobuo Ome, JP 54 902
Yamaguchi, Hizuru Akishima, JP 45 642

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