NAND flash memory with a programming voltage held dynamically in a NAND chain channel region
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United States of America Patent
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Feb 9, 2010
Grant Date -
May 17, 2007
app pub date -
Jan 9, 2007
filing date -
Sep 17, 2001
priority date (Note) -
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Abstract
Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltages even when the access lines are disconnected. In a memory have an array of NAND chains, the capacitance of the channel of each NAND chain can latch a voltage to either enable or inhibit programming. The bit lines can then be disconnected during programming of the group and be used for another memory operation. In one embodiment, the bit lines are precharged for the next verifying step of the same group. In another embodiment, two groups of memory cells are being programmed contemporarily, so that while one group is being programmed, the other group can be verified with the use of the bit lines.
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