Method and system for inspection optimization in design and production of integrated circuits

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United States of America Patent

PATENT NO 7665048
APP PUB NO 20080148195A1
SERIAL NO

11612439

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Abstract

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A method and apparatus for inspection optimization is provided. Inspection optimization improves the parametric and functional yield using optimized inspection lists for in-line semiconductor manufacturing metrology and inspection equipment.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95034

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Kevin San Jose, US 77 1256
Drege, Emmanuel Los Gatos, US 21 738
Jakatdar, Nickhil Los Altos, US 49 1891
Litvintseva, Svetlana San Jose, US 7 390
Miller, Mark A Pleasanton, US 248 4871
Raquel, Francis Danville, US 6 318

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