Method and device for classifying cells in a layout into a same environment and their use for checking the layout of an electronic circuit
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United States of America Patent
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Feb 16, 2010
Grant Date -
Mar 6, 2008
app pub date -
Aug 1, 2007
filing date -
Aug 1, 2006
priority date (Note) -
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Abstract
A method and a device can be used for checking the layout of an electronic circuit of a semiconductor component. For example, the method includes an automatic classification of cells in at least one layout into a cell database, and an automatic layout checker comparing the cell database to a layout to be checked.
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