Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
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United States of America Patent
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Feb 23, 2010
Grant Date -
Oct 25, 2007
app pub date -
Jun 25, 2007
filing date -
Aug 15, 2005
priority date (Note) -
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Abstract
The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.
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