Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
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United States of America Patent
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Feb 23, 2010
Grant Date -
Sep 20, 2007
app pub date -
May 4, 2007
filing date -
Dec 12, 2001
priority date (Note) -
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Abstract
A system for detecting and identifying the identity of a scrambling code is provided. According to one aspect of the system, a single scrambling code generator is used to generate a plurality of segments forming sequential chips of a master scrambling code. According to an embodiment, the segments are correlated in parallel with received signals to identify an associated base station. According to yet another aspect of the system, each of a plurality of correlators maintains a corresponding segment. According to an embodiment, for every sixteen chips, a new segment is introduced into one of the correlators, a segment is dropped from another correlator, segments are sequentially shifted or propagated through the remaining correlators, and concurrent correlations are performed by the correlators using their respective corresponding segments and newly received signals.
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