System and method for re-shuffling test case instruction orders for processor design verification and validation
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United States of America Patent
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Feb 23, 2010
Grant Date -
Mar 12, 2009
app pub date -
Sep 11, 2007
filing date -
Sep 11, 2007
priority date (Note) -
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Abstract
A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.
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