Semiconductor package having double layer leadframe
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United States of America Patent
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Mar 2, 2010
Grant Date -
Aug 31, 2006
app pub date -
Nov 14, 2005
filing date -
Nov 12, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A leadframe chip scale package includes a double leadframe assembly. The first leadframe has a central die paddle and peripheral leads, and the second leadframe, superimposed over the first leadframe in the package, has peripheral leads. The peripheral leads of both leadframes are situated in at least one row along an edge of the package, and in some embodiments in a row along each of the four edges of the package. The leads are patterned such that when the second leadframe is superimposed over the first leadframe, the leads do not contact each other; in a plan view, the leads of the first leadframe appear to be interdigitated with the leads of the second leadframe.
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