Pixel structure and TFT array drain connected to pixel electrode without connection line from drain to top electrode therebetween
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United States of America Patent
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Mar 9, 2010
Grant Date -
May 11, 2006
app pub date -
Mar 16, 2005
filing date -
Nov 11, 2004
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of common lines, a plurality of top electrodes, a plurality of connection lines and a plurality of pixel electrodes is provided. Wherein, each thin film transistor is disposed in one of the pixel areas and driven through the corresponding scan line and data line. Each thin film transistor includes a gate, a source and a drain. The drain of the thin film transistor is electrically connected to the corresponding top electrode by the corresponding connection line. Besides, the drain of the thin film transistor is electrically connected to the pixel electrode, and a portion of the connection line is not covered by the pixel electrode.
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