Semiconductor device, layout design method thereof, and layout design device using the same
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United States of America Patent
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Mar 16, 2010
Grant Date -
Jun 12, 2008
app pub date -
Dec 7, 2007
filing date -
Dec 8, 2006
priority date (Note) -
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Abstract
A semiconductor device having a multilayer structure, each layer including: a dummy pattern for ensuring a flatness thereof; a pad area in which a bonding pad is formed; an input-output circuit area in which an input-output circuit is formed, the input-output circuit area being adjacent to the pad area in plan view; and a dummy pattern confined area for forbidding an arrangement of the dummy pattern in every layer included in the semiconductor device, the dummy pattern confined area being provided between the pad area and the input-output circuit area in plan view.
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