US Patent No: 7,679,168
Number of patents in Portfolio can not be more than 2000
Printed circuit board with differential pair arrangement
Stats
-
Mar 16, 2010
Issued date -
Jul 21, 2006
filing date -
11/309,266
serial no -
In Force
status
Importance
Loading Importance Indicators...
Abstract
A printed circuit board (PCB) with a differential pair arrangement includes a mounting area for receiving a chip, a plurality of first pads located near one edge of the mounting area, a plurality of second pads located near an opposite edge of the mounting area, the first pads and the second pads are arranged for receiving pins of the chip. A pair of vias is used for connecting layers of the PCB. The second pads are located between the vias and the mounting area. A differential pair includes two signal traces, one of the signal traces is connected to one of the first pads and routed to one of the vias through the mounting area, the other of the signal traces is routed through the mounting area and connected to one of the second pads and then routed to the other one of the vias.
Loading the Abstract Image...
First Claim
Related Publications
Loading Related Publications...
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
|
|
|||
| 6,215,184 Optimized circuit design layout for high performance ball grid array packages | 15 | 1999 | |
| 6,323,116 Differential pair geometry for integrated circuit chip packages | 8 | 2000 | |
|
|
|||
| 7,227,254 Integrated circuit package | 1 | 2002 | |
|
|
|||
| 6,972,380 Printed wiring board having impedance-matched differential pair signal traces | 3 | 2004 | |
|
|
|||
| 5,639,989 Shielded electronic component assembly and method for making the same | 196 | 1994 | |
|
|
|||
| 6,777,802 Integrated circuit package substrate with multiple voltage supplies | 6 | 2002 | |
|
|
|||
| 6,384,342 Heat-resistant electronic systems and circuit boards with heat resistant reinforcement dispersed in liquid metal | 4 | 1999 | |
|
|
|||
| 7,361,846 High electrical performance semiconductor package | 2 | 2004 | |
|
|
|||
| 5,994,766 Flip chip circuit arrangement with redistribution layer that minimizes crosstalk | 116 | 1998 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Sep 16, 2013 |
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Sep 16, 2017 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Sep 16, 2021 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 3.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |