System and method for global circuit routing incorporating estimation of critical area estimate metrics
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United States of America Patent
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Mar 23, 2010
Grant Date -
Oct 16, 2008
app pub date -
Apr 11, 2007
filing date -
Apr 11, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.
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