High density trench MOSFET with reduced on-resistance

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United States of America Patent

PATENT NO 7687851
SERIAL NO

11285855

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Abstract

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A method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) cell includes the steps of opening a gate trench in a semiconductor substrate and implanting ions of a first conductivity type same as a conductivity type of a source region with at least two levels of implanting energies to form a column of drain-to-source resistance reduction regions below the gate trench. The method further includes steps of forming a gate in the gate trench and forming body and source regions in the substrate surrounding the gate trench. Then the MOSFET cell is covered with an insulation layer and proceeds with applying a contact mask for opening a source-body contact trench with sidewalls substantially perpendicular to a top surface of the insulation layer into the source and body regions. The method further includes a step of implanting ions of a second conductivity type opposite the first conductivity type with at least two levels of implanting energies to form a column of electrical field reduction regions below the source-body contact trench next to the column of drain-to-source resistance reduction regions to function as charge balance regions to the drain-to-source resistance reduction regions.

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Patent Owner(s)

  • M-MOS SEMICONDUCTOR SDN. BHD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hshieh, Fwu-Iuan Saratoga, US 163 5785

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