Single damascene structure semiconductor device having silicon-diffused metal wiring layer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 30, 2010
Issued Date -
N/A
app pub date -
Aug 28, 2003
filing date -
May 8, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Loading Importance Indicators... 
Abstract
In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
Loading the Abstract Image...
OK
First Claim
Family
Loading Family data...
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully