Method and system for model-based design and layout of an integrated circuit

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United States of America Patent

PATENT NO 7698666
APP PUB NO 20080163134A1
SERIAL NO

11648150

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Abstract

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Disclosed is a method, system, and computer program product for implementing model-based layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout. In effect, the parameters that are used for placement and routing are guided by the model data so that the layout can be formed with a high degree of manufacturability from the outset.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE BUILDING 5 SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brashears, Richard San Jose, US 13 64
Nequist, Eric Monte Sereno, US 28 292

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