Frequency locking structure applied to phase-locked loops
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United States of America Patent
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Apr 20, 2010
Grant Date -
Feb 25, 2010
app pub date -
Aug 19, 2008
filing date -
Aug 19, 2008
priority date (Note) -
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Abstract
A frequency locking structure applied to phase-locked loops (PLL) utilizes a common factor to reduce the difference between an output signal of oscillation and an input signal of reference for the jitter reduction of the input signal of reference. Moreover, a count value of clock signal is an input of a greatest-common-factor calculator to acquire an adaptive value and a feedback adaptive value for the common factor of a divider. Such a frequency locking structure both prevents the PLL from being in error about outputting frequency and dynamically adjusts the common factors for different purposes.
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