Packaging of integrated circuits with carbon nano-tube arrays to enhance heat dissipation through a thermal interface
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United States of America Patent
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Apr 27, 2010
Grant Date -
Jan 3, 2008
app pub date -
Aug 30, 2007
filing date -
Feb 3, 2003
priority date (Note) -
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Abstract
According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.
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