Via-first interconnection process using gap-fill during trench formation
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United States of America Patent
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Apr 27, 2010
Grant Date -
Jan 22, 2009
app pub date -
Jul 25, 2008
filing date -
Jul 17, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.
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