Three dimensional six surface conformal die coating

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7705432
APP PUB NO 20050224952A1
SERIAL NO

11016558

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
VERTICAL CIRCUITS SOLUTIONS INC10 VICTOR SQUARE SCOTTS VALLEY CA USA 95066

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Robinson, Marc San Jose, US 12 247
Vindasius, Al Saratoga, US 8 282

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation