Write-side calibration for data interface
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United States of America Patent
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Apr 27, 2010
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app pub date -
Apr 13, 2007
filing date -
Apr 21, 2006
priority date (Note) -
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Abstract
Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.
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